In recent years, a notebook personal computer and a desktop personal computer (hereinafter, each referred to as PC) compatible to a wide display horizontally longer than a conventional display have gained more in popularity. Each PC outputs video signals having various kinds of resolution such as resolution corresponding to the conventional display and resolution corresponding to the wide display.
FIG. 1 shows an example of a combination of resolution of a video signal and an aspect ratio that a currently representative PC supports. As shown in FIG. 1, there are various kinds of resolution for video signals, and horizontal resolution corresponding to vertical resolution is not limited to one kind of resolution.
For example, when a video signal output from the PC is input to a projector, and the projector displays a video, the projector must determine resolution of the input video signal. The video signal includes a vertical synchronization signal and a horizontal synchronization signal. This enables the projector to determine vertical resolution by detecting the number of vertical lines from the vertical synchronization signal and the horizontal synchronization signal. However, horizontal resolution corresponding to each vertical resolution is not necessarily one kind of resolution. It is therefore difficult to accurately determine horizontal resolution.
The video display device generates a dot clock to sample input video signals. Generally, the video display device includes a PLL (Phase Locked Loop; phase synchronization circuit. By changing the frequency division ratio of the PLL circuit, a frequency of the dot clock can be adjusted to be an integral multiple of a horizontal synchronization signal of the input video signal.
The video display device that has determined horizontal resolution of the input video signal can sample input video signals based on the dot clock of a frequency corresponding to the horizontal resolution. Accordingly, the video display device can correctly sample video signals. However, when the input video signals are sampled based on the dot clock of a frequency corresponding to the wrong horizontal resolution, the video display device cannot correctly sample video signals.
For example, Patent Literature 1 discloses a technology for determining horizontal resolution based on input video signals. In a video signal processing device disclosed in Patent Literature 1, resolution of all video signals is registered in a signal information table. The video signal processing device narrows down horizontal resolution of the input video signals based on the number of vertical lines of the input video signals. When sampling of A/D (analog/digital) conversion is not carried out by the dot clock of a frequency corresponding to the horizontal resolution of the input video signals, even if the same analog video signal is input, different digital video signals are output. Thus, the video signal processing device measures, for each narrowed-down horizontal resolution, the difference between digital data generated by sampling based on the dot clock of a frequency corresponding to the horizontal resolution and digital data generated by sampling based on the same dot clock after a certain period of time, and determines horizontal resolution, in which the difference is smallest, to be the horizontal resolution of the input video signals.
In the video display device, when the input video signal and the phase of the dot clock are not correctly adjusted, jittering or flickering occurs in the displayed image. Patent Literature 2 discloses a technology for adjusting the phase of a dot clock. FIG. 2A is an explanatory view showing a correctly adjusted state of the phase relationship between a video signal and the dot clock disclosed in Patent Literature 2. FIG. 2B is an explanatory view showing a shifted state of the phase relationship between the video signal and the dot clock disclosed in Patent Literature 2.
In the dot clock generated in the PLL circuit, jittering occurs on a time axis. Shaded parts of the dot clocks shown in FIGS. 2A and 2B indicate jitter widths (hereinafter, jitter areas) formed due to the influence of jitters at rising edges of the dot clocks. As shown in FIG. 2A, when the video signal and the dot clock match each other in phase, during sampling at the rising edge of the dot clock, the output value is constant wherever in the jitter area the rising edge is located. On the other hand, as shown in FIG. 2B, when a phase shift occurs between the video signal and the dot clock, the output value changes depending on where in the jitter area the rising edge is located.
For example, it is presumed that the video signals shown in FIGS. 2A and 2B are reversed black and white for each pixel, and pixel values are alternated between 0 and 255. When the video signal and the dot clock match each other in phase, the output value is alternated between 0 and 255. Thus, the absolute value of a difference in pixel value between adjacent pixels is always 255. On the other hand, when a phase shift occurs between the video signal and the dot clock, the output value fluctuates between 0 and 255. Thus, the absolute value of a difference in pixel value between adjacent pixels is smaller than 255.
Based on this relationship, the technology disclosed in Patent Literature 2 adjusts the phase of the dot clock so that the value obtained by converting differences in pixel values between adjacent pixels into absolute values and cumulatively adding the absolute values can be largest.